Barry Pangrle — extended biography

Barry started his career as an academic on the faculty in the ECE Department at UCSB and the Computer Science Department at Penn State University where he taught courses in Computer Architecture using Hennessey and Patterson and VLSI design as well as a course in neural networks using McClelland and Rumelhart’s Parallel Distributed Processing texts. At Penn State, his undergraduate students with no previous VLSI design experience were able to tape out small bit-sliced simple processors using MOSIS in one semester.

In 1994 Barry moved to Silicon Valley, initially managing the R&D for a team of exceptionally talented engineers, that brought a novel high-level design concept all the way to a fully released product that was used by Hitachi on many chips and FPGAs. From there he joined his first fabless semiconductor startup where he was one of the first ten employees and hired and led the design methodology team that implemented an efficient RTL C-based methodology for designing and verifying a multi-threaded processor that was presented at DAC in 2002.

He returned to Synopsys in 2002 to head up the Power Compiler and PrimePower power optimization and analysis teams. He grew the team and directed the development of the next generation Power Compiler code that cut the number of outstanding bugs in half and merged into the main code base ahead of schedule. The annual revenue for these products grew significantly during this period into the tens of millions of dollars.

Since then Barry has notably worked at Mentor Graphics (now Siemens EDA) as their in-house power expert working closely with customers and across BU R&D teams to set company strategy relative to power analysis, management and verification, at NVIDIA as a member of their power methodology team where he coded RTL to reduce micro-power spikes and improved on-chip power estimation leading to a 4% improvement in 3Dmark performance, and as a co-founder of energy-efficient HPC fabless semiconductor company Esperanto Technologies, where he was responsible for tools and methodologies as well as leading early IT efforts in setting up their offices and hybrid colocation center. He also created the RTL power analysis flow at SiFive and performed post-silicon analysis for their quad-core RISC-V Freedom Unleashed 740 used in their Unmatched development board.

An aspect of designing for high-performance, energy-efficient systems that he finds exciting is that it touches on all phases of the design and verification processes. Typically, the largest benefits are obtained at the architectural level and its important to track efficiencies at each successive stage, as well as the software and compiler components, all the way down to getting the most from the underlying characteristics of the transistors.

Barry has authored and co-authored many published reviewed papers and book chapters as well as online articles at Semiconductor Engineering. He is a senior member of the IEEE and a past general co-chair of the International Symposium on Low Power Electronics and Design (ISLPED) and has also served on numerous technical program committees for DAC, ICCAD, ISLPED, among others. He currently also serves as the Open Source Lead for the IEEE P1801 (UPF) Working Group.