Abacus Semiconductor has developed processors, accelerators and smart multi-homed memories that are intended to reduce complexity and cost while maintaining a performance lead over traditional solutions.

The most traditional product is a Server-on-a-Chip consisting of application processor cores and accelerators for typical database and web server applications. It can also be used as a frontend for the other processors and memory subsystems from Abacus Semiconductor. This chip allows server manufacturers to build a server from a very small number of components, while alleviating the need to use external RAID or ZFS accelerators or network function offload NICs (aka Smart NICs or Data Processing Units, DPUs). This processor offers a substantial cost reduction over traditional processors for standard server applications. Abacus Semiconductors' other processors and memory subsystems are targeting HPC. These processors and memories are designed with higher internal and external bandwidths than traditional solutions consisting of processors, PCIe- or CXL-attached accelerators and DDR4 or DDR5 DRAM DIMMs.

We have been using RISC-V since 2012. At this point in time, we have enough experience with it that we have re-implemented it in Verilog, i.e. we do not use the RocketChip CHISEL core. We have removed its limitations and added hardware support for virtualization, security and better caching and core interconnects. At the same time, we retained full ISA compatibility.

Our processors include all necessary firmware and software as well as APIs.

The areas of deployment are

and many more. Unlike other accelerators our processors have the I/O and memory bandwidth to sustain their performance and scalability. Our logical and physical address space is large enough to support 64 bit, 96 bit and 128 bit physical address spaces, and the coherency and security domains can span any subset of those. As a result, our processors, accelerators and smart multi-homed memory subsystems support GPT-n model generation, even if for GPT-4 an estimated 1 trillion parameters are needed.

Server-on-a-Chip

The Server-on-a-Chip is a many-core general-purpose processor. Its processor cores are all based on the open RISC-V instruction set architecture (ISA). This many-core processor enables server manufacturers to build a server from a single chip that includes 16 RISC-V processor cores (v1 prototype) as application processors, a dual-core RISC-V processor for RAID and ZFS offload, and a dual-core RISC-V processor for 10 and 100 Gbit/s LAN offload, as well as hardware accelerators for these functions, for our version 1 prototype. All RISC-V processor cores are 64-bit variants. The processor is clocked at 2 GHz and has a TDP of less than 65 W. It provides all of the standard interfaces expected from today's processors such as PCIe and DDR5 as well as one Universal High-Performance Interconnect/UHI™ port. It enables server manufacturers to build high-performance and cost-effective solutions for web services and database as well as high-transaction applications. A second version of this processor will double the number of processor cores and add an additional UHI port. This processor family makes up the ASC Legacy Support System, or ASC-LSS. The ASC-LSS family ties the existing infrastructure such as DDR3/4/5 memory, SAS/SATA/M.2 disks and PCIe Gen3 as well as networking through 10 and 100 GbE to the new architecture of the other ASC processors and accelerators. All versions of the ASC-LSS are referred to as the ASC29100 family.

Heterogeneous Random Access Memory

The Heterogeneous Random Access Memory (HRAM) consists of multiple hierarchies of memory and the associated memory controllers. It is a 1 TB or 4 TB random access memory with integrated memory controllers and caches. All versions connect to Abacus Semiconductor processors through its full-duplex UHI ports. The Heterogeneous Random Access Memory family features very high bandwidth, very high density, low latency and enhanced features such as autonomous memcopy ("Zero-Thread Memcopy" or ZTM™), auto or on-demand scrubbing, advanced parity checking and error detection and correction abilities, and many others. These memory subsystems are random access memories optimized for massively multi-threaded, multi-core host processors. They are multi-homed, i.e. they can connect to multiple Abacus Semiconductor processors. All address fields are 64 bit wide. Each Heterogeneous Random Access Memory uses 48 out of the available 64 address bits to future-proof the design for a total address space of 256 TB per chip. Unlike DRAM DIMMs our HRAM is scalable and shareable, and unlike HBM it is an external chip and as such adding HRAMs is a matter of a redesign of a server mainboard (PCB) instead of a redo of an ASIC. The ASC39100 has a rated capacity of 1 TB, whereas the ASC39200 has a rated capacity of 4 TB.

Application Processor

The Application Processor is a CPU with 64 RISC-V cores (v1 prototype) and 16 UHI ports. All RISC-V processor cores are 64-bit variants with hardware support for virtualization and vastly optimized internal interconnects. The ASC-AP is also referred to as the ASC29200. In a typical deployment, the ASC-AP is used with at least one ASC-LSS as an I/O frontend through one of its UHI ports. All other ports can be used in a mix-and-match configuration to connect to other Application Processors, Database Processors, Math Processors or Heterogeneous Random Access Memories. The target deployment scenarios of this processor are applications in which a strict centralized scheduling of tasks is performed by an application processor and the work is offloaded to other processors, coprocessors or specific accelerators. At this point in time, the Application Processor is based on the same processor die as the Database Processor, but the firmware is different. In the future, the hardware of these two processor families may diverge.

Database Processor

The Database Processor is a CPU with 64 RISC-V cores (v1 prototype) and 16 UHI ports. All RISC-V processor cores are 64-bit variants with hardware support for virtualization and vastly optimized internal interconnects. The ASC-DP is also referred to as the ASC29300. In a typical deployment, the ASC-DP is used with at least one ASC-LSS as an I/O frontend through one of its UHI ports. All other ports can be used to connect to other Database Processors and Heterogeneous Random Access Memories, and at least one Application Processor for orchestration and for optional connection to additional legacy I/O through the Server-on-a-Chip or ASC-LSS. The target deployment scenarios of this processor are large-scale in-memory database applications. At this point in time, the Database Processor is based on the same processor die as the Application Processor, but the firmware is different. In the future, the hardware of these two processor families may diverge.

Math Processor

The Math Processor is a massively parallel processor that accelerates all openCL and openACC applications, replacing handwritten C or assembly code for better performance, easier portability and drastically simplified maintenance while providing better performance and scalability, along with higher precision and accuracy. Our processors can be used in traditional HPC such as FEA/FEM, solving n-body problems, for Computational Fluid Dynamics (CFD), mechanical, thermal and electrical simulations including signal integrity and power integrity problems, modeling and a variety of other applications, and in more modern HPC fields such as in AI for training and inference. For applications that rely on CUDA we support all current CUDA function calls and translate them into our native math functions. The ASC-MP is also referred to as the ASC29400 family.

Support/Downloads

We are working on an automated support infrastructure for downloads, updates, FAQs and general customer support as well as for a bug reporting system.