Even the most recent traditional memory subsystems (DDR5, the upcoming DDR6 and even HBM3) rely on outdated architectures that work best with single-core, single-processor hosts. As we all know any modern computer deploys multi-core multi-threaded processor cores, and therefore the old paradigm does not apply any more. Multi-core processors and even more so massively parallel processors are hampered by the design philosophy of current memory subsystems. Abacus Semiconductor has identified that weakness and developed a Heterogeneous Random Access Memory that supports all compatible host processors irrespective of how many cores they contain (multiple, many or massively parallel cores) with our Universal High-Performance Interconnect/UHI™. Abacus Semiconductors' HRAM does not have these limitations. All connections are point-to-point connections and not multi-drop buses, and thus they maintain performance with a full-duplex bandwidth of up to 224 GB/s per port.

The Multi-Homed Heterogeneous Random Access Memory (HRAM) is a 1 TB or 4 TB multi-homed random access memory with integrated memory controllers and caches. Its four full-duplex Universal High-Performance Interconnect/UHI™ ports connect to Abacus Semiconductor processors and accelerators as well as to other HRAMs. These random access memories are optimized for massively multi-threaded, multi-core host processors and associated workloads. They are multi-homed, i.e. they can connect to multiple Abacus Semiconductor processors and accelerators to facilitate data sharing while keeping the data coherent.

Our Heterogeneous Random Access Memory is based on the idea that a processor or an accelerator does not need a memory controller, and that all memory controllers should reside on the memory module or chip or SoC itself. That logic makes the interface to the processor universal and agnostic to the memory type.

The Heterogeneous Random Access Memory family features very high bandwidth, very high density, low latency and enhanced features such as autonomous memcopy, automatic or on-demand scrubbing, advanced parity checking and error detection and correction abilities, and many others. The HRAM is a truly autonomous and smart memory subsystem. It supports Zero Thread MemCopy/ZTM™ while making sure that all tags — including security — are obeyed and preserved.

All HRAM-internal address fields are 64 bit wide. 48 bit out of those are used to future-proof the design for a total address space of 256 TB per HRAM.

At the same time the DRAM Controller and its associated SSTL-2 interface can be removed from the CPU, offloading power consumption and reducing its thermal footprint by a few Watts. That power can be used to integrate an HBM Controller for use as an L4 Cache on the CPU substrate.

The ASC39100 has a rated capacity of 1 TB, whereas the ASC39200 has a rated capacity 4 TB.