Abacus Semiconductor has developed a Server-on-a-Chip based on the open RISC-V instruction set architecture (ISA). This Server-on-a-Chip with traditional PCIe and DRAM (DDR5) interfaces as well as hardware-supported RAID and ZFS as well as network filtering functions similar to pfSense allows server manufacturers to build a server from a single chip, excluding the DRAM DIMMs or our HRAM or a combination of both and the BIOS/UEFI chip. This many-core processor includes 16 RISC-V processor cores as application processor cores, a dual-core RISC-V processor for RAID and ZFS offload, and a dual-core RISC-V processor for 10 and 100 Gbit/s LAN offload, as well as hardware accelerators for these functions (v1 prototype). All RISC-V processor cores are 64-bit variants. The processor is clocked at 2 GHz and has a TDP of less than 35 W. It provides all of the standard interfaces expected from today's processors such as PCIe and DDR5 as well as a Universal High-Performance Interconnect/UHI™ port. Its 4 DDR5 channels allow for a very high performance and large DRAM main memory. The memory can be optionally fully encrypted, at a very low incremental latency over a non-encrypted memory. It also provides a built-in Flash Controller to support DDR Flash on the DIMM Bus. It enables server manufacturers to build high-performance and cost-effective solutions for web services and database as well as high-transaction applications. All I/O offload cores come with an application-specific OS that is specifically optimized for this purpose and that we maintain. We call this processor family the ASC Legacy Support System, or ASC-LSS, as it supports all current interfaces to DRAM and to I/O while providing a bridge to more modern and higher-bandwidth interfaces such as UHI. All versions of the ASC-LSS are referred to as the ASC29100 family.

The ASC-LSS can be used standalone or as a I/O frontend or coprocessor for the rest of the ASC product family using UHI, and for the same purpose for any other processor architecture if used as a PCIe-attached coprocessor. The processor cores inside the Server-on-a-Chip are based on the open RISC-V instruction set architecture and therefore are ISA-compatible with RISC-V, including RocketChip. However, we found that we had to optimize performance, scalability and security of the open-source implementation of it, and as a result, we rewrote much of the design. We have added virtualization HW to the CPU cores and the IOMMU so that they can be used in fully virtualized environments.

These processors include all necessary I/O such as SAS and SATA ports, USB 3, 3.1 and 3.1 Gen2 and a combined PCIe/CXL Root Complex so that future interfaces as well as high-performance graphics can be added at any time. If used as a PCIe-attached coprocessor, the PCIe/CXL interface can be configured to be a PCIe/CXL Endpoint. The 4 integrated DRAM Controllers support up to 64 TB of DDR5 DRAM. Each DRAM Controller supports 3 DIMM slots. With current DDR5 DIMMs (max 512 GB), the maximum addressable memory size is 6 TB. Memory bandwidth scales with the number of DRAM channels that are populated in parallel. This processor supports secure boot from an SPI Flash memory, and it provides full resiliency against failed firmware updates as well as redundancy while allowing in-service firmware updates and upgrades. We call those features Assured Firmware Integrity/AFI™ and Resilient Secure Boot/RSB™. M.2 Flash modules are supported natively including booting from these.

These comprehensive Server-on-a-Chip processors include firmware (including the bootloader), FreeBSD as an Operating System, all necessary APIs and drivers, as well as a firmware update tool. RAID and ZFS (mass storage) as well as IPv4, IPv6, TCP, UDP and ICMP (network functions) offload as well as filtering functions (similar to opnSense) are supported through hardware and firmware. A heavily modified fork of Veracrypt runs on the mass storage cores and allows for real-time full disk encryption, using the built-in dedicated mass storage crypto engines. All drivers for FreeBSD and Linux are included. A hypervisor allows LINUX applications for RISC-V to run natively after a recompile with the provided LLVM/CLANG compiler as part of the SDK and IDE.

These processors are ideal for applications that create high transactional loads such as web or file servers and database servers including in-memory databases such as ScyllaDB, and as a frontend for our other processors. For applications that require very high numerical performance please use our math processors in conjunction with the Server-on-a-Chip processor, and for extremely high transaction-count applications we suggest using our Application Processor or Database Processor with the ASC-LSS as a frontend.